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Electronics Nanocharacterization

Lehigh has state-of-the-art capabilities in nanoelectronic facilities, such as electron beam lithography and focused ion beam nanofabrication. Lehigh has developed nanoscale devices, sensors, and circuits which have achieved operation at ultra-low voltages. In fact, these voltages are the lowest reported to date. Applications are in nonvolatile semiconductor memories (e.g. "smart" cards and cell phones) and solar powered electronics. Research on a "Bio-Chip" the width of a human hair to sequence the human genome is an exciting area of current Lehigh nanoelectronics activity.


Nanoelectronics Laboratory Measures



Electrical Parameter Measurements

I-V Measurement (HP 4145)

Drain Current (IDS) vs. Gate Voltage (VGS)
Drain Current (IDS) vs. Drain Voltage (VDS)

C-V Measurement (HP 4192)

Capacitance (CGB) vs. Gate Voltage (VGB)

Derived Results (SPICE Parameters)

I-V

Transconductance (Gm)
Threshold Voltage (VTH)
Flat Band Voltage (VFB)
Doping Concentration (NA)
Fermi Potential (ØF)
Transistor Gain (ß0)
Surface Roughness Coefficient (QS)
Series Resistance (RS)
Mobility (un, up)

C-V

Oxide Thickness (TOX)
Flat Band Voltage (VFB)

LabVIEW™

Create graphically oriented PC programs for automated control of laboratory equipment
Data displayed on PC screen and stored in text files



Charge Pumping and Linear Voltage Ramp Techniques

Charge Pumping Technique:

Determine interface and near interface traps densities
Study the device reliability to endurance stress of thin oxides

Linear voltage ramp (LVR) or Split-C-V technique:

Characterize the mobile ions in the oxide layer when performed at elevated temperatures
Extract independently inversion charge to determine the effective device mobility
Extract thickness of multi-layer thin gate dielectric devices, such as NVSM devices



Characterization of Nonvolatile Semiconductor Memories
Flexible Test Setup - National Instruments DAQ Card
Wide range of applied voltages and timing
Program device using Fowler-Nordheim Tunneling or Hot Electron Injection
LabVIEW™ interface for data display/storage

 

Procedure:
Set temperature for test
Write or Erase device
Detection circuit extracts Threshold Voltage (VTH) at times ranging from 3 hours to several days

Results:
Determine time limit of charge retention
Test charge retention at elevated temperatures ranging from 22 to 400°C
Test charge retention after millions of Erase/Write cycles for device endurance (stressing)
Extract trap densities and energies in Nitride charge storage films using retention data at varied temperatures
Test programming efficiency at varied voltages

 

Nanoelectronics Laboratory Measures

Electrical Parameter Measurements

Charge Pumping and Linear Voltage Ramp Techniques

Characterization of Nonvolatile Semiconductor Memories
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