Fully Refereed Archival Publications


Xiaochen Guo, Mahdi Nazm Bojnordi, Qing Guo, and Engin Ipek, “Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM based Main Memories,” in the IEEE Transactions on Computers (TC), 2018.


Yuan Zeng, Kevin Devincentis, Yao Xiao, Zubayer Ibne Ferdous, Xiaochen Guo, Zhiyuan Yan, and Yevgeny Berdichevsky, “A Supervised STDP-based Training Algorithm for Living Neural Networks,” arXiv preprint arXiv: 1710.10944, 2017.


Chris Garman, Xiaochen Guo, and Michael Spear, “A Study of Unnecessary Write Backs,” in Proceedings of the International Symposium on Memory Systems (MEMSYS), Alexandria, VA, October 2017.


Yuan Zeng and Xiaochen Guo, “Long Short Term Memory based Hardware Prefetcher,” in Proceedings of the International Symposium on Memory Systems (MEMSYS), Alexandria, VA, October 2017.


Chao Zhang and Xiaochen Guo, “Enabling Efficient Fine-Grained DRAM Activations with Interleaved I/O,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Taiwan, July 2017.


Xiaochen Guo, Aviral Shrivastava, Michael Spear, and Gang Tan,Languages Must Expose Memory Heterogeneity,” in Proceedings of the International Symposium on Memory Systems (MEMSYS), Alexandria, VA, October 2016.


Qing Guo, Xiaochen Guo, Yuxin Bai, Ravi Patel, Engin Ipek, and Eby G. Friedman, Resistive TCAM Systems for Data-intensive Computing,” in IEEE Micro special issue on Alternative Compute Designs and Technologies (IEEE Micro), October 2015.


Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, and Eby G. Friedman,Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing,” in the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), March 2015.


Isaac Richter, Kamil Pas, Xiaochen Guo, Ravi Patel, Ji Liu, Engin Ipek, and Eby G. Friedman, “Memristive Accelerator for Extreme Scale Linear Solvers,” the Government Microcircuit Applications & Critical Technology Conference (GOMAC), St. Louis, MO, March 2015.


Qing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek, and Eby G. Friedman, “AC-DIMM: Associative Computing with STT-MRAM,” in Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.


Qing Guo, Xiaochen Guo, Yuxin Bai, and Engin Ipek, “A Resistive TCAM Accelerator for Data Intensive Computing,” in Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011.


Xiaochen Guo, Engin Ipek, and Tolga Soyata,Resistive Computation: Avoiding the Power Wall with Low-Leakage, STT-MRAM Based Computing,” in Proceedings of the 37th International Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 2010.


Bo Xiao, Liandong Liu, Xiaochen Guo, and Ke Xu, “Modeling the IPv6 Internet AS-level Topology,”Physica A, 388(2009): 529-540. doi: 10.1016/j.physa.2008.10.034.



Book Chapters


Engin Ipek, Qing Guo, Xiaochen Guo, and Yuxin Bai, “Resistive Memories in Associative Computing,” in Emerging Memory Technologies: Design, Architecture, and Applications, Yuan Xie (Editor), Springer, July 2013.



Patents


Eby Friedman, Isaac Richter, Xiaochen Guo, Mohammad Kazemi, Kamil Pas, Ravi Patel, Engin Ipek, and Ji Liu, “Resistive Memory Accelerator,” US20170040054 A1, Feb 9, 2017.


Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, and Vijayalakshmi Srinivasan, “Processor with Memory-Embedded Pipeline for Table-Driven Computation,US9740496 B2, Aug 22, 2017.


Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, and Vijayalakshmi Srinivasan, “Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM),” US9431084 B2, Aug 30, 2016.


Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, and Vijayalakshmi Srinivasan, “Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM),” US9406368 B2, Aug 2, 2016.


Xiaochen Guo and Arun Jagatheesan, “Page Merging for Buffer Efficiency in Hybrid Memory Systems,” US8874827 B2, Oct 28, 2014.